1. Field of the Invention
The present invention relates generally to a semiconductor device and a manufacturing method thereof, and particularly to a CMOS semiconductor device having a STI (Shallow Trench Isolation).
2. Description of the Related Art
In developing STI technology for a CMOS semiconductor device, there are two main objects to be addressed in conjunction with miniaturization of semiconductor device elements. One is suppressing interwell leakage, and the other is controlling stress generated from the STI that is applied to the active region.
In the following, the interwell leak current generated between a p-well and an n-well is described. As is shown in FIG. 1, for example, in a case where a drain voltage is applied to an n-type drain of an NMOS device, the interwell leak current refers to the leak current that flows from the n-type drain of this NMOS device via a STI to an n-well of a PMOS device adjacent to this NMOS device. With the miniaturization of the semiconductor device, the leak current may increase owing to the reduction in length of the leak path through which the leak current flows.
In response to such a problem, techniques are disclosed that involve enlarging the bottom portion of the STI in order to extend the leak path so that leak current generation may be suppressed (e.g., see Japanese Laid-Open Patent Publication No. 2002-270684 and Japanese Laid-Open Patent Publication No. 2002-43413). However, the disclosed techniques do not address the other object, namely, controlling the stress generated from the STI upon miniaturization of semiconductor device elements.
The other object to be addressed in developing STI technology is controlling the stress generated from the STI. Compressive stress from STI implant material reduces mobility particularly in an NMOS semiconductor, and thereby, a nitride film that generates tensile stress is often used as a liner film at the STI side wall in order to reduce the compressive stress from the STI (e.g., see Japanese Laid-Open Patent Publication No. 2003-273206).
FIG. 2 is a diagram illustrating an exemplary STI structure having a nitride film liner. In FIG. 2, the inner wall of a trench formed through anisotropic dry etching, for example, is lined with a nitride film liner 101, and an oxide film 102 is employed to fill in the trench covered by the nitride film liner 101 to realize a STI 110. In this example, tensile stress is applied to the channel region so that the decrease in mobility may be alleviated.
Also, it is noted that tensile stress in the channel direction is preferably applied to improve mobility of the NMOS semiconductor. Accordingly, a structure is disclosed in which an oxidation preventive film made of nitride material, for example, is formed on the STI side wall adjacent to a NMOS whereas the STI side wall adjacent to an PMOS does not have the oxidation preventive film formed thereon (e.g., see Japanese Laid-Open Patent Publication No. 2003-158241).